IEEE 1149.1 JTAG Test Standard

The IEEE 1149.1 boundary scan standard is a set of rules incorporated into advanced integrated circuits. IEEE 1149.1 allows chip and board tests to be generated automatically by software and applied to boards through a simple 4 wire bus. This reduces the need for expensive bed-of-nail testers and allows the pin pitch of integrated circuits to shrink below the size that an array of test nails can access. If all the chips on the board are 1149.1 compliant, it is possible to do a complete shorts-and-opens test on the board, run test vectors, and even sample the state of the board while it is running via the 4 wire bus.

The 4 wire bus can even be driven from the parallel port of a PC, allowing designers to run extensive tests on their design from their desktop. Thousands of components now incorporate IEEE 1149.1, from simple gates to complex microprocessors.

IEEE 1149.1 is also referred to as JTAG, after the European Joint Test Action Group, which invented the first versions of this interface.

IEEE 1149.1 is a digital-only standard. Since many systems combine analog and digital, a new standard for mixed-signal testing is being developed, IEEE 1149.4. KLIC is working with the 1149.4 committee, and designed a test chip to test the new 1149.4 standard against real world constraints.

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last revision Jan 11, 2013